This chapter documents the Backend for the 80x86 microprocessor family.

1 Legal
=======

This module is written in 2005-2006,2011,2015-2016 by Frank Wille and is
covered by the vasm copyright without modifications.

2 Additional options for this module
====================================

This module provides the following additional options:

‘-cpudebug=<n>’
     Enables debugging output.

‘-m8086’
     Generate code for the 8086 CPU.

‘-mi186’
     Generate code for the 80186 CPU.

‘-mi286’
     Generate code for the 80286 CPU.

‘-mi386’
     Generate code for the 80386 CPU.

‘-mi486’
     Generate code for the 80486 CPU.

‘-mi586’
     Generate code for the Pentium.

‘-mi686’
     Generate code for the PentiumPro.

‘-mpentium’
     Generate code for the Pentium.

‘-mpentiumpro’
     Generate code for the PentiumPro.

‘-mk6’
     Generate code for the AMD K6.

‘-mathlon’
     Generate code for the AMD Athlon.

‘-msledgehammer’
     Generate code for the Sledgehammer CPU.

‘-m64’
     Generate code for 64-bit architectures (x86_64).

3 General
=========

This backend accepts 80x86 instructions as described in the Intel
Architecture Software Developer's Manual.

   The target address type is 32 bits.  It is 64 bits when the x86_64
architecture was selected (‘-m64’).

   Instructions do not need any alignment.  Data is aligned to its
natural alignment by default.

   The backend uses MIT-syntax!  This means the left operands are always
the source and the right operand is the destination.  Register names
have to be prefixed by a '%'.

   The operation size is indicated by a 'b', 'w', 'l', etc.  suffix
directly appended to the mnemonic.  The assembler can also determine the
operation size from the size of the registers being used.

4 Extensions
============

Predefined register symbols in this backend:

   − 8-bit registers: ‘al cl dl bl ah ch dh bh axl cxl dxl spl bpl sil
     dil r8b r9b r10b r11b r12b r13b r14b r15b’
   − 16-bit registers: ‘ax cx dx bx sp bp si di r8w r9w r10w r11w r12w
     r13w r14w r15w’
   − 32-bit registers: ‘eax ecx edx ebx esp ebp esi edi r8d r9d r10d
     r11d r12d r13d r14d r15d’
   − 64-bit registers: ‘rax rcx rdx rbx rsp ebp rsi rdi r8 r9 r10 r11
     r12 r13 r14 r15’
   − segment registers: ‘es cs ss ds fs gs’
   − control registers: ‘cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10
     cr11 cr12 cr13 cr14 cr15’
   − debug registers: ‘dr0 dr1 dr2 dr3 dr4 dr5 dr6 dr7 dr8 dr9 dr10 dr11
     dr12 dr13 dr14 dr15’
   − test registers: ‘tr0 tr1 tr2 tr3 tr4 tr5 tr6 tr7’
   − MMX and SIMD registers: ‘mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7 xmm0 xmm1
     xmm2 xmm3 xmm4 xmm5 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11 xmm12 xmm13
     xmm14 xmm15’
   − FPU registers: ‘st st(0) st(1) st(2) st(3) st(4) st(5) st(6) st(7)’

   This backend extends the selected syntax module by the following
directives:

‘.code16’
     Sets the assembler to 16-bit addressing mode.

‘.code32’
     Sets the assembler to 32-bit addressing mode, which is the default.

‘.code64’
     Sets the assembler to 64-bit addressing mode.

5 Optimizations
===============

This backend performs the following optimizations:

   − Immediate operands are optimized to the smallest size which can
     still represent the absolute value.

   − Displacement operands are optimized to the smallest size which can
     still represent the absolute value.

   − Jump instructions are optimized to 8-bit displacements, when
     possible.

6 Known Problems
================

Some known problems of this module at the moment:

   − 64-bit operations are incomplete and experimental.

7 Error Messages
================

This module has the following error messages:

   − 2001: instruction not supported on selected architecture
   − 2002: trailing garbage in operand
   − 2003: same type of prefix used twice
   − 2004: immediate operand illegal with absolute jump
   − 2005: base register expected
   − 2006: scale factor without index register
   − 2007: missing ')' in baseindex addressing mode
   − 2008: redundant %s prefix ignored
   − 2009: unknown register specified
   − 2010: using register %%%s instead of %%%s due to '%c' suffix
   − 2011: %%%s not allowed with '%c' suffix
   − 2012: illegal suffix '%c'
   − 2013: instruction has no suffix and no register operands - size is
     unknown
   − 2015: memory operand expected
   − 2016: you cannot pop %%%s
   − 2017: translating to %s %%%s,%%%s
   − 2018: translating to %s %%%s
   − 2019: absolute scale factor required
   − 2020: illegal scale factor (valid: 1,2,4,8)
   − 2021: data objects with %d bits size are not supported
   − 2022: need at least %d bits for a relocatable symbol
   − 2023: pc-relative jump destination out of range (%lld)
   − 2024: instruction doesn't support these operand sizes
   − 2025: cannot determine immediate operand size without a suffix
   − 2026: displacement doesn't fit into %d bits

